Design of High Speed 32 Bit Truncation-Error- Tolerant Adder
نویسندگان
چکیده
In this project, we had proposed architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has always to be expected. By adopting and introducing a novel error–tolerant adder in VLSI design. This error-tolerant adder is easy to develop the accuracy out puts and at the same time it achieves tremendous improvements in both the power consumption and speed performance. By comparing previous or conventional counter parts and errortolerant adder the proposed ETA is to be attain more than 74% improvements in power-delay products. One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors. Key words— High speed arithmetic, error tolerant technique, power dissipation, Digital Signal Processing (DSP), adder cells, high-speed integrated circuits, low-
منابع مشابه
Design and Verification of Performance of 32 Bit High Speed Truncation- Error -Tolerant Adder
In this study, we have proposed an architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel errortolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tre...
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